z80380 CPU user's manual

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The word Add, Subtract, Compare, and signed and unsigned Multiply instructions take one input operand from the HL register and the other from a 16-bit register, from the instruction itself, or from memory using Indexed Except for Increment, Decrement, and Extend Sign, all the instructions in this group set the CPU flags to reflect the computed result. Table 5-10. 16-Bit Arithmetic Operation Instruction Name Format src/ dst Add With Carry (Word) ADC HL,src ADCW [HL],src ADD HL,src ADD IX,src ADD IY,src ADDW [HL,]src ADD SP,nn ANDW [HL,]src CPLW [HL] CPW [HL,]src DEC[W] dst DIVUW [HL,]src EXTSW [HL] INC[W] dst MULT [HL,]src MULTUW [HL,]src NEGW [A] ORW [HL,]src SBC HL,src SBCW [HL],src SUB HL,(nn) SUBW [HL,]src SUB SP,nn XORW [HL,]src src src src src src src src src dst src dst src dst dst src src dst src src src src src src src Add (Word) Add to Stack Pointer AND Word Complement Accumulator Compare (Word) Decrement (Word) Divide Unsigned Extend Sign (Word) Increment (Word) Multiply Word Signed Multiply Word Unsigned Negate Accumulator OR Word Subtract with Carry (Word) Subtract (Word) Subtract from Stack Pointer Exclusive OR BC DE HL SP IX IY nn (nn) (IX+d) (IY+d) √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ X X X X X X X X Note: that the instructions with “X” at the rightmost column is affected by Extended mode.

Table 5-4. 16-Bit and 32-Bit Load, Exchange, PUSH/POP Group Instructions Instruction Name Format Note Exchange Word/Long Word Registers Exchange Byte/Word Registers with Alternate Bank Exchange Register Pair with Alternate Bank EX dst,src EXX EX RR,RR’ See Table 5-5 Exchange Index Register with Alternate Bank EXXX EXXY EXALL LD dst,src LDW dst,src POP dst PUSH src SWAP dst Exchange All Registers with Alternate Bank Load Word/Long Word Registers POP PUSH Swap Contents of D31-D16 and D15-D0 Table 5-5.

Another variant, the TSTIO instruction, does a logical AND to the instruction operand with the internal I/O location specified by the C register and changes the CPU flags without modifying CPU registers or memory. The remaining instructions in this group form a powerful and complete complement of instructions for transferring blocks of data from memory to Internal I/O locations. The operation of these instructions is very similar to that of the block move instructions described earlier, with the exception that one operand is always an Internal I/O location whose address also increments or decrements by one automatically, Also, the address of the other operand (a memory location) is incremented or decremented.

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