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In Verilog, blocks are called modules, and contain both interface and implementation in the same code. SystemC separates the interface/implementation similar to VHDL. cpp file) is used for the architecture. Blocks communicate via ports/pins and signals or wires in traditional HDLs. In SystemC, modules are interconnected using either primitive channels or hierarchical channels. Both types of channels connect to modules via ports. The powerful ability to have interchangeable channels is implemented through a component called an interface.
This is typically 28 SystemC: From The Ground Up accomplished by providing an environment variable named SYSTEMC, and ensuring the Makefile. 7 If using gcc, the command probably looks something like this: g++ –I$ (SYSTEMC) /include \ –L$ (SYSTEMC) /lib–$ (ARCH) –lsystemc \ $(SRC) Figure 3-3. Partial gcc Options to Compile and Link SystemC The downloadable examples available from our website include Makefiles setup for Linux and gcc. Please refer to your C++ tool manuals for more information. For the hardcore engineer types, you now have everything you need to compile and run a Hello_SystemC program; we have provided the obligatory program in Figure 3-4.
Much greater detail will be presented in subsequent chapters. SystemC addresses the modeling of both software and hardware using C++. Since C++ already addresses most software concerns, it should come as no surprise that SystemC focuses primarily on non-software issues. The primary area of application for SystemC is the design of electronic systems, but SystemC has been applied to non-electronic systems5. 1 C++ Mechanics for SystemC We would like to start with the obligatory Hello_SystemC program but first let’s look at the mechanics of compiling and executing a SystemC program or model.